| 摘要 |
A comparator having a small number of logic circuits and an improved operating speed is provided, where the comparator includes m number of bit comparators, each connected between a first node and a second node, comparing each corresponding bit between the first data and the second data, and connecting or disconnecting the first node and the second node, a charge unit connected between the first node and a first voltage and charging the first node with the first voltage, and a power connection controller disconnecting the second node and a second voltage in a first mode in response to a predetermined control signal and connecting the second node and the second voltage in a second mode, wherein the first node is charged with the first voltage in the first mode and the voltage level of the first node is output as a comparison result in the second mode.
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