摘要 |
<p>A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuit comprises a plurality of circuit stages connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other. In each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.</p> |
申请人 |
TIMELAB CORPORATION;CARLEY, ADAM, L.;ALLEN, DANIEL, J.;MANDRY, JAMES, E. |
发明人 |
CARLEY, ADAM, L.;ALLEN, DANIEL, J.;MANDRY, JAMES, E. |