| 摘要 |
PROBLEM TO BE SOLVED: To reduce man-hour by verifying layout data whether wiring accords with a constraint value, by calculating the constraint value of wiring width based on the wiring allowable current of an integrated circuit. SOLUTION: The setting part of wiring width restrictions in an integrated circuit is selected in a processing 101 of a restriction part selecting means, and a circuit simulation is executed in a processing 102 of a simulation means so that it may be verified whether the allowable current value of wiring width restrictions of the processing 101 has been exceeded. When it is exceeded, a required wiring width is determined by a processing 103 of a constraint value determination means based on a current value, and connecting information is created from circuit diagram data 108 in a processing 104 of a connecting information creating means. In a processing 105 of a rule creating means, a verifying rule 111 is created which defines a verifying wiring width for every network based on the wiring width determined by the processing 103. In a processing 107 of a layout verifying means, it is verified whether the layout data accord with the wiring width of determined by the verifying rule on the basis of a connecting information 110, the verifying rule 111, and layout data 112 created by a processing 106 of the layout creating means. COPYRIGHT: (C)2006,JPO&NCIPI
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