| 摘要 |
A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined threshold. A low power comparator (LPTC) detects the drop and starts up the QSO which in turn awakens the controller. The controller determines what the reason for the awakening is, quickly responds to the exigent circumstance and then turns the QSO off to thereby conserve power and put itself (QSO) back to sleep. Disclosures are provided for the QSO and a first calibration subsystem used to maintain QSO output frequency within a desired range. Disclosures are provided for the LPTC and a second calibration subsystem used to set its trigger threshold. Disclosure of a novel DAC within the LPTC is also provided.
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