发明名称 Bifurcated thread scheduler in a multithreading microprocessor
摘要 A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.
申请公布号 US2006179279(A1) 申请公布日期 2006.08.10
申请号 US20050051997 申请日期 2005.02.04
申请人 MIPS TECHNOLOGIES, INC. 发明人 JONES DARREN M.;KINTER RYAN C.;KISSELL KEVIN D.;PETERSEN THOMAS A.
分类号 G06F9/30 主分类号 G06F9/30
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