发明名称 CHARACTERISTIC ADJUSTMENT CIRCUIT FOR LOGIC CIRCUIT, ITS METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT USING IT
摘要 PROBLEM TO BE SOLVED: To suppress variation of a delay time of a logic circuit using a MOS transistor. SOLUTION: A phase difference is detected by a phase comparator 2, between oscillation output of a ring oscillator 1 using a delay element which is constituted by the same MOS transistor as that of an internal MOS type logic circuit requiring characteristic adjustment, and prescribed reference clock input 10. A back gate voltage of the MOS transistor is generated and controlled by a back gate voltage generation circuit 3 corresponding to the phase difference. Consequently, the characteristics including the delay time of the internal logic circuit can be constantly and uniformly controlled. Particularly, a logic circuit element requires adjustment of the delay time in a semiconductor IC, and is actually used as the delay element 100 constituting the ring oscillator 1. Eventually, a difference of effect due to type of logic circuit to back gate voltage control can be reduced. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006211064(A) 申请公布日期 2006.08.10
申请号 JP20050017560 申请日期 2005.01.26
申请人 NEC CORP 发明人 YAMANOBUTA HISASHI
分类号 H03K5/13;H03K3/03 主分类号 H03K5/13
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