Programmable bank/timer address folding in memory devices

摘要

A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.