CLOCK SUPPLY CIRCUIT, AND SEMICONDUCTOR SYSTEM AND ITS DESIGNING METHOD

摘要

PROBLEM TO BE SOLVED: To provide a clock supply circuit which has a gated lock function and can suppress clock skew due to temporal deterioration of a transistor.

SOLUTION: A selector 31 of a clock gate circuit GC passes a clock signal when an enable signal EN has a high level and passes the output signal of a toggle flip-flop 21 when the enable signal EN has a low level. The toggle flip-flop 21 inverts and outputs a stored value each time the enable EN rises. Each time the enable signal EN falls to the low level, logical levels of buffers 15 and 16 and flip-flops F3 and F4 are switched alternately between a low-level fixed state and a high-level fixed state. It is considered that a high-level fixed period and a low-level fixed period are equal to each other and buffers 13 and 14 and buffers 15 and 16 are equally influenced by delay deterioration to suppress clock skew.

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