| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve the driving ability of a transistor by optimizing the lay out of the active region of the transistor, the source and drain length (X) from an active edge in the drain to a gate edge. <P>SOLUTION: It is a semiconductor device 1 in which a plurality of NMOS transistors 21 are arranged in the direction of a gate length of a transistor and a plurality of PMOS transistors 41 are arranged in the direction of the gate length of the transistor and a plurality of PMOS transistors 41 are arranged by a column other than the column in which the above NMOS transistors 21 are arranged. The active region 22 of the plurality of the NMOS transistors 21 is set to one formed in the direction of the gate length of the above NMOS transistor 21 from the active region. A shield gate 61 is formed between the above NMOS transistors 21, and the plurality of the PMOS transistors 41 each has an active region 42 separated every PMOS transistor 41. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
