METHOD OF MAKING A PLANAR DOUBLE-GATED TRANSISTOR

摘要

A silicon layer (16) interposed between the top silicon nitride layer (SiN) (20) and a silicon germanium layer (SiGe) (14) which in turn is over a thick oxide (BOX) (12) is selectively etched to leave a stack with a width that sets the gate length. A sidewall insulating layer (28) is formed on the SiGe layer (14) leaving the sidewall of the Si (16) layer exposed. Silicon (30, 32) is epitaxially grown from the exposed silicon sidewall (16) to form in-situ-doped silicon source/drain regions (30, 32). The nitride layer (20) is removed using the source/drain regions (30) as a boundary for an upper gate location. The source/drain regions (30, 32) are coated with a dielectric (36). The SiGe layer (14) is removed to provide a lower gate location (46). Both the upper and lower gate locations (46) are filled with metal to form upper and lower gates (50) for the transistor (10).