发明名称 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
摘要 |
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
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申请公布号 |
US2006176739(A1) |
申请公布日期 |
2006.08.10 |
申请号 |
US20060391662 |
申请日期 |
2006.03.28 |
申请人 |
LEE PETER W;HSU FU-CHANG;TSAO HSING-YA;MA HAN-REI |
发明人 |
LEE PETER W.;HSU FU-CHANG;TSAO HSING-YA;MA HAN-REI |
分类号 |
G11C11/34;G11C16/04;G11C16/10;G11C16/14;H01L21/8247;H01L27/115 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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