| 摘要 |
<P>PROBLEM TO BE SOLVED: To adjust a filer coefficient of a filer circuit used for stabilizing the jitter accuracy of a PLL circuit while decreasing man-hours necessary for the adjustment. <P>SOLUTION: The PLL circuit 2 is formed in a semiconductor chip 1, the filter circuit 3 whose filter coefficient is switchable, a switching element 4 for switching the filter coefficient of the filter circuit 3 and a register 5 for latching a signal for turning on/off the switching element 4 are also formed, the signal for turning on/off the switching element 4 so as to optimize the filter coefficient of the filter circuit 3 is set to the register 5, and the filter coefficient of the filter circuit 3 is adjusted by turning on/off the switching element 4 on the basis of the signal set to the register 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
