发明名称 WIRING PATTERN FORMING METHOD AND MASK USED THEREIN
摘要 <P>PROBLEM TO BE SOLVED: To provide a pattern forming method capable of securing the wide margin of exposure in test pattern formation and a mask used for the execution. <P>SOLUTION: As a mask for the exposure of the first time, rectangular areas for which a macro pattern block width 3101 is 7 &mu;m and a macro pattern block height 3102 is 500 &mu;m are formed at a prescribed pitch on a chromium film 3100 formed on a glass substrate (Fig. (a)). Inside the area, the bundle of fine wiring &le;0.1 &mu;m exists as the object of process evaluation. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006210821(A) 申请公布日期 2006.08.10
申请号 JP20050023830 申请日期 2005.01.31
申请人 NEC ELECTRONICS CORP;RENESAS TECHNOLOGY CORP 发明人 MATSUBARA YOSHIHISA;MATSUURA SEIJI;KOBAYASHI HIROMASA
分类号 H01L21/027;G03F1/00;G03F1/68;G03F7/20;H01L21/3205;H01L21/768;H01L23/52;H01L23/522 主分类号 H01L21/027
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