| 摘要 |
PROBLEM TO BE SOLVED: To provide a controller preventing the erroneous operation of a CPU due to the rewriting of an operation program in an RAM, and preventing the input of a command to control the RAM from being suppressed. SOLUTION: A comparator circuit 51 judges whether to execute writing protection to an SDRAM 40 from an address signal and a control signal. When it is judged that the writing protection should be executed by the comparator circuit 51, the result is outputted to a gate circuit 52 as a WPACC signal 414. When the WPACC signal 41 is active, a gate circuit 52 compulsorily makes active a DQMB signal 412. Thus, it is possible to prevent data from being written in the SDRAM 40, and to input a command to control the SDRAM 40. COPYRIGHT: (C)2006,JPO&NCIPI
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