| 发明名称 |
Method for combining via patterns into a single mask |
| 摘要 |
In a damascene process of fabricating an interconnect structure in an integrated circuit, a method for removing separate via layers is disclosed herein, which includes combining the via layers into a single mask.
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| 申请公布号 |
US7087350(B2) |
申请公布日期 |
2006.08.08 |
| 申请号 |
US20030720887 |
申请日期 |
2003.11.24 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD. |
发明人 |
WANG HSIANG WEI |
| 分类号 |
G01F9/00;G03F1/14;H01L23/48 |
主分类号 |
G01F9/00 |
| 代理机构 |
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