发明名称 |
Test arrangement for testing semiconductor circuit chips |
摘要 |
The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).
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申请公布号 |
US7088122(B2) |
申请公布日期 |
2006.08.08 |
申请号 |
US20040922005 |
申请日期 |
2004.08.19 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
HARTMANN UDO;CANAUD THIERRY |
分类号 |
G01R31/28;G11C29/48;H03K19/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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