| 摘要 |
A method and circuit to adjust timing between received differential data and clock signals to compensate for differences between transmission paths of data and clock signals. According to one embodiment, a timing adjustment circuit includes a decoder, a differential delay stage and a converter stage. The decoder is arranged to select one of the differential tri-state buffers, which provides the signal with a selected delay to a differential-to-single-ended converter. The converter provides properly a timing-adjusted signal to other circuits for further processing. Two current sources may be employed instead of resistive loads for the converter stage resulting in increased operating frequency and decreased power dissipation.
|
