| 摘要 |
Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a type of access mode (e.g., interleaved or sequential), and performing scrambling operations based on chip organization (e.g., x4, x8, or x16) a bank location being accessed. Similar operations may be performed (in reverse order) in a read path, to assemble data to be read out of a device.
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