发明名称 |
DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays |
摘要 |
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line.
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申请公布号 |
US2006172483(A1) |
申请公布日期 |
2006.08.03 |
申请号 |
US20050051119 |
申请日期 |
2005.02.03 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
FORBES LEONARD |
分类号 |
H01L21/8238;H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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