发明名称 Drain extended PMOS transistor with increased breakdown voltage
摘要 A semiconductor device ( 102 ) that includes a drain extended PMOS transistor (CT 1 a) is provided, as well as fabrication methods ( 202 ) therefore. In forming the PMOS transistor, a drain ( 124 ) of the transistor is formed over a region ( 125 ) of a p-type upper epitaxial layer ( 106 ), where the region ( 125 ) of the p-type upper epitaxial layer ( 106 ) is sandwiched between a left P-WELL region ( 130 a) and a right P-WELL region ( 130 b) formed within the p-type upper epitaxial layer ( 106 ). The p-type upper epitaxial layer ( 106 ) is formed over a semiconductor body ( 104 ) that has an n-buried layer ( 108 ) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.
申请公布号 US2006170056(A1) 申请公布日期 2006.08.03
申请号 US20050047418 申请日期 2005.01.31
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 PAN SHANJEN;PENDHARKAR SAMEER;TODD JAMES R.
分类号 H01L29/76 主分类号 H01L29/76
代理机构 代理人
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