| 摘要 |
A simulation device for an integrated circuit according to the present invention comprises a first memory unit, a first input unit, a second memory unit, an execute unit, a second input unit and an output unit. A net list of a particular path in inter-cell paths in the integrated circuit comprising a plurality of synchronizing circuit cells is stored in the first memory unit. The first input unit appends a variation information relating to gate lengths, gate widths and the like of transistors to the net list stored in the first memory unit. The variation net list to which the variation information is appended by the first input unit is stored in the second memory unit. The execute unit executes a simulation using the variation net list stored in the second memory unit to thereby calculate a delay variation distribution. The second input unit appends a circuit information to the path. The output unit sets and outputs a design margin of the circuit based on the delay variation distribution calculated by the execute unit and the circuit information appended by the second input unit.
|
