| 摘要 |
A method for manufacturing integrated circuits having at least one silicon-germanium heterobipolar transistor is provided, wherein a dielectric applied to the surface of the wafer is planarized. The dielectric having elevations produced by the thickness of monocrystalline semiconductor regions structured below the dielectric, wherein the semiconductor regions are covered by a first stop layer, in that for the purpose of planarization, a second stop layer is applied to the dielectric. Subsequently, a planarization layer, which in the area of each elevation forms a smaller layer thickness than outside the area of each elevation, is applied to the second stop layer. Thereafter, the planarization layer is removed in the area of each elevation and the second stop layer is removed in the area of each elevation. Then, the wafer is polished chemically-mechanically in such a way that the dielectric in the area of each elevation is made thinner at least up to the first stop layer.
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