发明名称 256 MEG DYNAMIC RANDOM ACCESS MEMORY
摘要 PROBLEM TO BE SOLVED: To reduce a load current with respect to a boosted voltage by an output buffer. SOLUTION: The output buffer circuit is provided with a plurality of output drive transistors serially connected between a first voltage source and an earth, an output terminal which responds to the serially connected output drive transistor, a latch for receiving data output to the output terminal, a logical circuit for controlling the output drive transistor to drive the voltage of the output terminal at a high or low potential indicating the logical state of the output data in response to the latch, a boot capacitor for supplying additional voltages to some output drive transistors, a holding transistor for connecting the boost capacitor to a second voltage source in response to the logical circuit, and a self-timer type circuit path connected between the holding transistor and the boot capacitor. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006202482(A) 申请公布日期 2006.08.03
申请号 JP20060065104 申请日期 2006.03.10
申请人 MICRON TECHNOLOGY INC 发明人 KEETH BRENT;BUNKER LAYNE G;DERNER SCOTT J;TAYLOR RONALD L;MULLIN JOHN S;BEFFA RAYMOND J;ROSS FRANK F;KINSMAN LARRY D
分类号 G11C11/401;G11C11/409;G11C5/02;G11C5/06;G11C11/407;G11C11/4074;G11C11/4076;G11C11/4097;G11C29/04;G11C29/14;H01L21/8242;H01L27/108;H03K19/0175 主分类号 G11C11/401
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