发明名称 |
High density bitline selection apparatus for semiconductor memory devices |
摘要 |
A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.
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申请公布号 |
US2006171215(A1) |
申请公布日期 |
2006.08.03 |
申请号 |
US20050046101 |
申请日期 |
2005.01.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DAWSON JAMES W.;PLASS DONALD W.;REYER KENNETH J. |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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