发明名称 Fehlertolerantes Computersystem, Verfahren zur Resynchronisierung desselben und zugehöriges Resynchronisierungs-Programm
摘要 <p>In a lock-step synchronism fault-tolerant computer system including a plurality of computing modules (100, 200, 300) having a processor (101, 102, 201, 202, 301, 302) and a memory (104, 204, 304) in which each computing module (100, 200, 300) processes the same instruction string in synchronization with each other. When detecting disagreement in a state of access to an external bus among the respective processors in each computing module (100, 200, 300), if no fault is detected in the system including each computing module (100, 200, 300), processing of resuming operation in synchronization is executed with respect to each computing module (100, 200, 300) after generating an interruption to all the processors to execute delay adjustment for making a state of instruction execution among computing modules (100, 200, 300) be coincident. <IMAGE></p>
申请公布号 DE60302184(T2) 申请公布日期 2006.08.03
申请号 DE2003602184T 申请日期 2003.07.10
申请人 NEC CORP. 发明人 AINO, SHIGEYUKI;YAMAZAKI, SHIGEO
分类号 G06F11/16;G06F11/18;G01R31/317;G01R31/3185;G06F1/12;G06F11/00;G06F11/10;G06F11/20;G06F11/273;G06F12/08;G06F12/14;G06F12/16;G06F13/00 主分类号 G06F11/16
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