| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a floating gate memory array which can store a plurality of bits for each cell and which is operated with a page mode. <P>SOLUTION: A multiplex level floating gate memory array (10) includes word lines (18) connected to memory cells along a row in the array, and a bit lines (12) connected along a column. Also, the array includes a word line power source (27) supplying selectively word line voltage corresponding to respective threshold voltage of the memory cells. A plurality of bit latches form a page buffer (11). The bit latch is coupled to a corresponding bit line, and has first and second states. The bit latch includes circuits (213-215) changing the bit latch from the first state to the second state in accordance with a signal on a corresponding bit line generated in accordance with word line voltage on a selected word line being equal or larger than threshold voltage of a memory cell on a corresponding bit line connected to a selected word line. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
