发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
摘要 PROBLEM TO BE SOLVED: To prevent erosion of pad portions on TEGs, and to enhance solderability of pad portions of a real device and shear strength, after the formation of solder bumps. SOLUTION: A third layer wiring M3 in a chip region CA and the third layer wiring M3 in a scribe region SA of a semiconductor wafer are formed with a TiN-film M3a, Al alloy film M3b, and TiN-film M3c. A second pad portion PAD2 on a rewiring 49 in the chip region CA is cleaned, or an Au film 53a is formed thereon by electroless plating method. After forming the Au film 53a, retention inspection is carried out further; and subsequently, after forming an Au film 53b, solder bump electrodes 55 are further formed, thereafter. As a result, erosion by the plating solution or the like of the first pad portion PAD1, formed of the third layer wiring M3 in the scribe area SA where TEGs, are formed is prevented by the TiN-film M3c. In addition, wettability of solder of the second pad portion PAD2 and the shear strength after the solder bump formation thereof can be enhanced by the Au film 53a, 53b. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006203215(A) 申请公布日期 2006.08.03
申请号 JP20060013356 申请日期 2006.01.23
申请人 RENESAS TECHNOLOGY CORP 发明人 YAJIMA AKIRA;YAMAMOTO KENICHI;ABE HIROMI
分类号 H01L23/52;H01L21/3205;H01L21/66;H01L21/768;H01L21/822;H01L21/8247;H01L23/12;H01L27/04;H01L27/10;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L23/52
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