发明名称 |
Control of voltages during erase and re-program operations of memory cells |
摘要 |
A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.
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申请公布号 |
US2006171213(A1) |
申请公布日期 |
2006.08.03 |
申请号 |
US20060334205 |
申请日期 |
2006.01.18 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
DEL GATTO NICOLA;LISI CARLO;DI VINCENZO UMBERTO;TURBANTI PAOLO |
分类号 |
G11C5/14 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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