| 摘要 |
An SRAM cell 1 includes inverters 10, 20 , N-type FETs 32, 34, 36, 38 , word lines 42, 44 , bit lines 46, 48 , and voltage applying circuits 50, 60 . The voltage applying circuits 50, 60 apply a voltage V<SUB>dd </SUB>to the word lines 42, 44 at the time of a read operation of the SRAM cell 1 . The voltage applying circuits 50, 60 apply a voltage (V<SUB>dd</SUB>+alpha) to the word lines 42, 44 at the time of a write operation of the SRAM cell 1 . Here, alpha> 0 . Namely, the SRAM cell 1 is configured in such a manner that a voltage applied to word lines 42, 44 at the time of the write operation is higher than at the time of the read operation.
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