| 摘要 |
CMOS static RAM based memory system, which reduces power consumption and increases operation speed by disconnecting cell power supply during write operation. Additional transistors are provided between sources of the SRAM cell transistors and supply voltage or ground voltage connection. These are switched off during write, in order to interrupt a dynamic current path to supply or to ground. Additionally, implementation of inductive elements into the power supply can help to reduce current spikes during switching. |
