STORING APPARATUS AND METHOD FOR CONTROLLING THE SAME

摘要

In SDR mode (S/D = H), the logic level transition of a data status precedence determination signal (RDYO) is outputted to an output terminal (O) in accordance with an internal clock (CKI). A ready signal (RDY) is outputted in synchronism with an internal clock (CKI) following the logic level transition of the data status precedence determination signal (RDYO). In DDR mode (S/D = L), a toggle signal is outputted to the output terminal (O) in accordance with the internal clock (CKI) following the logic level transition of the data status precedence determination signal (RDYO). A strobe signal (DQS) is outputted in synchronism with an internal clock (CKI) following the internal clock (CKI) following the logic level transition of the data status precedence determination signal (RDYO). The ready signal (RDY) in the SDR mode and the strobe signal (DQS) in the DDR mode are outputted from a data status notifying terminal (X).