| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit by which a stable high speed operation is possible even at low voltage. <P>SOLUTION: A clock buffer circuit 2 outputs a differential clock signal with offset having threshold voltage of a MOS transistor as offset voltage to latch circuits 1a, 1b. The latch circuits 1a, 1b switch a data through operation and a data holding operation to an input signal by operation of the MOS transistor having the threshold voltage by the differential clock signal with offset and output differential signals. The latch circuit 1a inputs an input differential signal, performs a data through operation/data holding operation by the differential clock signal with offset and supplies a differential signal to be output to the latch circuit 1b. The latch circuit 1b performs the data holding operation/data through operation on the supplied signal by a differential clock signal with offset with the opposite phase to the differential clock signal with offset to be supplied to the latch circuit 1a and outputs the resultant signal as an output differential signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
