发明名称 Electronic circuit design method, simulation apparatus and computer-readable storage medium
摘要 An electronic circuit designing method analyzes noise with respect to a wiring pair, and automatically corrects the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise.
申请公布号 US7086018(B2) 申请公布日期 2006.08.01
申请号 US20030456679 申请日期 2003.06.09
申请人 FUJITSU LIMITED 发明人 ITO NORIYUKI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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