发明名称 |
Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption |
摘要 |
A clock control apparatus for a memory controller comprises an interface unit which processes a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supplied to the memory controller. A power-saving control unit controls both a clock signal of an internal circuit of the memory controller and a clock enable signal of the SDRAM in response to a control signal supplied from the interface unit.
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申请公布号 |
US7085941(B2) |
申请公布日期 |
2006.08.01 |
申请号 |
US20030414013 |
申请日期 |
2003.04.16 |
申请人 |
FUJITSU LIMITED |
发明人 |
LI JIANG |
分类号 |
G06F1/26;G06F12/00;G06F1/32;G06F12/06 |
主分类号 |
G06F1/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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