| 摘要 |
A first delay circuit receives a sampling clock obtained by multiplying detected frequency of reference clock patterns and outputs delay clocks from first delay stages, respectively. Recording frequency of the sampling clock is not obtained using the reference clock patterns but obtained using received addresses. A disk driving apparatus obtains the number of the first delay stages to be used which correspond to one cycle of the obtained recording frequency and necessary for phase adjustment of the sampling clock, and disables not-used first delay stages. Any of the delay clocks is selected and at least one of regenerating operation to read data from a disk media and recording operation to write data thereto is executed in synchronization with the selected delay clock. Consequently, the number of delay stages to be disabled can be obtained with simple control, reducing power consumption of circuits for adjusting phases of the sampling clocks.
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