发明名称 Display device having SRAM built in pixel
摘要 Disclosed is a technology of further reducing power consumption while a display device having an SRAM built therein is being driven based on data held in the SRAM. A power source voltage control circuit is provided in a power source voltage generating unit for supplying a power source voltage to a data driver and a scan driver of the display device. During a period when graphic data held in the SRAM is supplied to a pixel and a display is performed, the supply of the power source voltage from the power source voltage control circuit is stopped, and operations of the data driver and the scan driver are stopped.
申请公布号 US7084851(B2) 申请公布日期 2006.08.01
申请号 US20010989027 申请日期 2001.11.21
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YAMASAKI NOBUO
分类号 G02F1/133;G09G3/36;G09G3/20 主分类号 G02F1/133
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