Size reduction techniques for vital compliant VHDL simulation models

摘要

A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file ( 310 ) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file ( 314 ) containing the super generics for every instance of every logic gate in the logic model.