发明名称 Method and arrangement for extracting capacitance in integrated circuits having non manhattan wiring
摘要 A method of extracting capacitance for a first wire segment is disclosed. The method approximates a non orthogonal first section of interconnect wiring containing the first wire segment by using an orthogonal second section of interconnect wiring. The method determines an estimated capacitance of the non orthogonal first section of interconnect wiring by using the orthogonal second section of interconnect wiring. The method adds a correction factor to the estimated capacitance to generate a modeled capacitance value for the non orthogonal first section of interconnect wiring.
申请公布号 US7086021(B2) 申请公布日期 2006.08.01
申请号 US20040998085 申请日期 2004.11.26
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 TEIG STEVEN;CHATTERJEE ARINDAM
分类号 G06F17/50 主分类号 G06F17/50
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