| 摘要 |
<P>PROBLEM TO BE SOLVED: To properly vary speeds of data write processing and data read processing. <P>SOLUTION: On receipt of a grade designation signal for designating a grade from a set unit 11, a controller 3 of a semiconductor memory unit 1 executes logic block assignment processing so that the data write processing and the data read processing can be executed in parallel to a flash memory chip CP of which the number corresponds to a grade designated by the received grade designation signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
