发明名称 |
ALLOYED UNDERLAYER FOR MICROELECTRONIC INTERCONNECTS |
摘要 |
Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material. |
申请公布号 |
WO2006063272(A3) |
申请公布日期 |
2006.07.27 |
申请号 |
WO2005US44699 |
申请日期 |
2005.12.07 |
申请人 |
INTEL CORPORATION;JOHNSTON, STEVEN;DOMINGUEZ, JUAN |
发明人 |
JOHNSTON, STEVEN;DOMINGUEZ, JUAN |
分类号 |
H01L23/532;H01L21/768 |
主分类号 |
H01L23/532 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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