发明名称 Cascade-type variable-order delta-sigma modulator
摘要 A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to n<SUP>th </SUP>stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n-1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.
申请公布号 US2006164274(A1) 申请公布日期 2006.07.27
申请号 US20060338651 申请日期 2006.01.25
申请人 NAKAKITA MASATO;INUKAI FUMIHITO;KOBAYASHI HITOSHI 发明人 NAKAKITA MASATO;INUKAI FUMIHITO;KOBAYASHI HITOSHI
分类号 H03M3/00 主分类号 H03M3/00
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