| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller that controls the timing of memory access, thereby reducing the overhead of the memory access, and increasing the speed of data transfer, and a high-speed data transfer method. SOLUTION: The memory controller is provided with an FIFO part 110 serving as a temporary storage circuit that takes up the difference between the bus width of a system bus B01 transferring data from a CPU 101 and the bus width of a memory bus B05 connecting an SDRAM 105 to a control LS 104. The burst transfer of the data stored in the FIFO part 110 is carried out according to a CPU start signal sent from a timing control part 113 to a command control part 114. COPYRIGHT: (C)2006,JPO&NCIPI
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