| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transfer control device capable of preventing an increase in the occupation ratio of a memory bus at the time of the DMA transfer of data through an input and output bus and the memory bus between an input and output device connected to the input and output bus and a memory connected to the memory bus. SOLUTION: This data transfer control device 1 for performing the DMA transfer of data between the I/O device 6 connected to the I/O bus 10 and an SDRAM 5 connected to an SDRAM bus 9 comprises an FIFO memory 1 buffering the transfer rate difference between the I/O bus 10 and the SDRAM bus 9. When data of the SDRAM 5 are DMA-transferred to the I/O device 6, the data of the SDRAM 5 are burst-transferred to and stored in the FIFO memory 11 through the SDRAM bus 9 at the point of time when the DMA transfer is permitted. In response to a transfer request from the I/O device 6, the data stored in the FIFO memory 1 are single-transferred to the I/O device 6 through the I/O bus 10. COPYRIGHT: (C)2006,JPO&NCIPI
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