发明名称 |
Delay time correction circuit, video data processing circuit, and flat display device |
摘要 |
The present invention is applied to, for example, a liquid crystal display device having a driving circuit integrally formed on an insulating substrate, and makes it possible to effectively avoid a variation in delay time in a logical circuit using TFTs or the like by inserting dummy data (DD) into input data (D 1 ) and forcedly switching the logical level of the input data (D 1 ) at a predetermined timing during a quiescent period (T 2 ) in which the input data is held at a constant logical level.
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申请公布号 |
US2006164364(A1) |
申请公布日期 |
2006.07.27 |
申请号 |
US20040564473 |
申请日期 |
2004.07.27 |
申请人 |
MURASE MASAKI;NAKAJIMA YOSHIHARU;KIDA YOSHITOSHI |
发明人 |
MURASE MASAKI;NAKAJIMA YOSHIHARU;KIDA YOSHITOSHI |
分类号 |
G09G3/36;H03K5/13;H03K3/356;H03K19/0185 |
主分类号 |
G09G3/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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