发明名称 SAMPLE-AND-HOLD CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit capable of improving a sampling precision. SOLUTION: In a first operation mode, voltage in which offset voltage VOFST is subtracted from signal voltage VIN inputted to an input terminal Tin is applied to a capacitor 1. In a second operation mode, voltage VSMP held in the capacitor 1 is inputted to an operational amplifier OP1. Thereby, in the second operation mode, voltage in which the offset voltage VOFST is added to the voltage VSMP held in the capacitor 1 is outputted from the operational amplifier OP1. At this time, since the voltage VSMP in which the offset voltage VOFST is subtracted from the signal voltage VIN is held in the capacitor 1, voltage in which the offset voltage VOFST is added to the above mentioned voltage is almost equal to the signal voltage VIN inputted to the input terminal Tin in the first operation mode. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006196105(A) 申请公布日期 2006.07.27
申请号 JP20050007551 申请日期 2005.01.14
申请人 SONY CORP 发明人 KAWABE AZUMA
分类号 G11C27/00;H03M1/12 主分类号 G11C27/00
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