Register file gating to reduce microprocessor power dissipation

摘要

A circuit arrangement and method of controlling power dissipation utilize a register file ( 60 ) with power dissipation control capabilities through a banked register design coupled with enable logic ( 62, 82 ) that is configured to selectively disable unused banks ( 70 ) of registers by selectively gating off clock ( 74 ), address ( 76 ) and data ( 78 ) inputs supplied thereto.