| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory having a bit line load provided with automatic bit line precharge and equalization. SOLUTION: A bit line load 380 is coupled to a pair of bit lines and provided with bipolar pull-up transistors 389 and 403, P type transistors 390 and 404, a NAND logic gate 395 and a P type equalizing transistor. The NAND logic gate 395 detects a differential voltage on the paired bit lines and generates an equalization signal. When a write control signal reports the end of a write cycle, the equalization signal starts precharge and equalization of the paired bit lines. COPYRIGHT: (C)2006,JPO&NCIPI
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