| 摘要 |
FIELD: digital pulse engineering. ^ SUBSTANCE: proposed device designed for executing full synchronization function for potential and/or input synchronized digital impulse signal (generation of synchronized signal and its sync signal) by means of continuous input train of clock pulses for building synchronizing devices (synchronous memory automations) for entering asynchronous instructions or data and for data exchange, for instance between two synchronous devices, each using its inherent clock frequency, has flip-flops 1- 3, NOT gate 4, EXCLUSIVE OR gates 5, 6, clock input 11, digital synchronized signal input 12, NOR gates 7, 8, OR gate 9, as well as AND gate 10; first output of device functions as sync signal output and second one, as synchronized signal output. ^ EFFECT: minimized length of zero or one phase limited only by response of hardware components. ^ 1 cl, 1 dwg |
