发明名称 Phase locked loop circuit, electronic device including a phase locked loop circuit and method for generating a periodic signal
摘要 A phase locked loop (PLL) circuit ( 1 ) comprising a loop input (11); a phase detector section ( 2 ) for detecting a phase difference between an input signal and a reference signal. The phase detector section ( 2 ) has a detector input connected to the loop input, a reference input and a detector output for outputting a signal related to the phase difference. A controlled oscillator ( 4 ) is connected with an input to the detector output and an oscillator output is connected to a loop output ( 12 ). The PLL has a feedback circuit which connects the oscillator output to the reference input, wherein the feedback circuit includes a device ( 7;71 - 74 ) having a transfer function with at least one zero.
申请公布号 US2006165206(A1) 申请公布日期 2006.07.27
申请号 US20040517181 申请日期 2004.12.07
申请人 EIKENBROEK JOHANNES WILHELMUS 发明人 EIKENBROEK JOHANNES WILHELMUS T.
分类号 H03D3/24;H03L7/10;H03L7/093;H03L7/18;H03L7/183;H03L7/185;H03L7/197 主分类号 H03D3/24
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