| 摘要 |
<p>A delay buffer includes a first shift register (50) receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an effective bit width of the input data. A first delay line (56) receives the shifted data from the first shift register while a second delay line (58) of equal length to the first delay line receives the shift signal. A second shift register (60) receives the output from the first delay line and receives the output of the second delay line on a shift signal input port (62). The second shift register then left shifts the data contained therein according to the shift signal.</p> |
